1. Field of the Invention
The present invention relates to a VLSI clocking methodology which uses both global overlapping and global or locally generated non-overlapping clocks, and more particularly, to a clocking system which selectively uses non-overlapping clocks to eliminate race conditions, selectively uses overlapping clocks for performance enhancement, and combines conditional signals with the clock signals.
2. Description of the Prior Art
The performance of very large scale integration (VLSI) systems has been improved by designing hardware which can handle greater clock frequencies. However, as the clock frequencies to such circuits are increased, increased efforts must be made to prevent performance degradation as a result of clock skew and the like. Unfortunately, since pipelined data processing systems generally use global clocks, which are generally a pair of differential symmetric clocks generated by a centralized clocking circuit, the skew and the rise/fall times of the clocking signals received by the respective pipelined circuits are poorly controlled. Thus, if the skew is large, slow clock signal fall times result which, for fast circuits, causes errors in the pipeline. Such errors are herein referred to as clock signal races and are characterized by pipeline situations in which data in one stage "sneaks" through to a subsequent stage before the proper clocking signal is received. As known to those skilled in the art, lost clock edges as a result of signal skew may lead to such errors.
Conventional techniques having overcome such clock signal race problems by using non-overlapping clock signals, which are typically differential clock signals in which one clock signal has a rising edge which occurs after a falling edge of the other clock signal and a falling edge which occurs before a rising edge of the other clock signal. Such signals prevent clock signal races in a pipelined circuit by deactivating a subsequent stage before data is allowed to propagate through the current stage. While such a clocking system prevents data from "sneaking" through to the next stage, it does so at significant performance cost due to the "dead" time between clock edges.
Global overlapping clocks generally provide timing advantages with respect to non-overlapping clocks in that there is no dead time between a falling edge of one clock signal and the rising edge of the other clock signal. As a result, early clock edges may be received which allow improved system performance of the pipelined circuits. Global overlapping clocks are also generally easier to distribute to the circuitry without closely controlling the clock skew caused by time/phase shifts. However, as just noted, if the clock skew is large, race conditions may be created which may cause information to be lost when only global overlapping clocks are used for clocking the pipelined circuits.
In order to prevent such race conditions and the resultant loss of data, quadrature clocking systems have been developed for use in pipelined circuits. Such quadrature clocking systems do not have the performance disadvantages of non-overlapping clocking systems and typically comprise two sets of overlapping clocks which are provided by two pairs of global clock drivers (or buffers). The extra set of overlapping clocks are offset with respect to the first set by approximately 90.degree. (i.e., they are shifted by 90.degree. with respect to the first set of clock signals) such that a minimum amount of overlap time can be used to prevent races between respective stages of the pipelined circuits. However, enough overlap must be provided to allow a minimum time to set the latches of the pipelined circuits. The four clock edges of the quadrature clocking signals can then be applied to the respective stages of the pipelined circuits as appropriate. This allows the system to keep data moving without allowing data to "sneak" through a stage to before the appropriate clock edge is received.
Although a quadrature clocking system is generally quite effective at eliminating race conditions, such a clocking system requires that two extra clocking signals be routed to the respective chips and that extra buffer space be provided for the clocking signals. In addition, quadrature clocks comprised of overlapping clock signals are still susceptible to the skew problems of global overlapping clocks noted above without the benefits of early edges.
In pipelines or portions of pipelines which utilize both conditional signals to regulate the flow of data and the clock signals, twice the number of gates are used, one for the clock signal and one for the conditional signal. This decreases the speed of the pipeline and increases the power consumed.